This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-333578, filed Oct. 31, 2000.
The present invention relates to a superconducting device and a method of manufacturing the same, particularly, to a superconducting device using an oxide superconductor and a method of manufacturing the same.
It is expected that an oxide superconductor will be utilized in a technical field requiring a high speed operation such as a super-high speed logic arithmetic device or a communication infrastructure. For realizing the utilization of the oxide superconductor, it is said to be of a high priority to establish at an early date a method of manufacturing a Josephson device that is a basic constituting element.
Josephson devices of a laminated type, a ramp edge type, a grain boundary junction type, and a step edge type are known to the art. Each of these Josephson devices is constructed such that a plurality of oxide thin films including a superconductor layer are laminated one upon the other. In the manufacturing process of the Josephson device, after the formation of one or some of the oxide thin films, etching and annealing processes are applied to the resultant structure. As a result, a non-superconductor layer is formed to constitute an interface between a first superconductor layer and a second superconductor layer. Alternatively, defects or dislocations are introduced between the first superconductor layer and the second superconductor layer so as to form an interface.
The construction of the interface highly influences the characteristics of the Josephson device that is finally obtained. Therefore, it is necessary to control with a high accuracy the defects and the dislocation density in the interface. However, the prior art gives rise to the following problem in conjunction with such a process. The problem will now be described, with the forming process of a ramp edge type junction, which is a typical type of junction, taken as an example.
In the forming process of a ramp edge type junction, which does not use a ground plane, in the first step, a superconductor layer used as a base electrode and an insulation layer are successively formed on a substrate so as to obtain a two-layer film. The substrate is generally made of, for example, SrTiO3, MgO, Laxe2x80x94Srxe2x80x94Alxe2x80x94Taxe2x80x94O oxide, NdGaO3, LaAlO3, or YSZ (Yttrium Stabilized Zirconia). On the other hand, each of the base electrode and a counter electrode referred to herein later is made of, for example, Yxe2x80x94Baxe2x80x94Cuxe2x80x94O oxide, Nbxe2x80x94Baxe2x80x94Cuxe2x80x94O oxide, Bixe2x80x94Srxe2x80x94Caxe2x80x94Cuxe2x80x94O oxide, Tixe2x80x94Baxe2x80x94Cuxe2x80x94O oxide or (Ba, K)BiO3 oxide. In this case, the base electrode is made of YB2Cu3O7 or NdBa2Cu3O7.
In a second step, a resist pattern is formed on the insulation layer by using a photolithography technique, followed by patterning the insulation layer by an ion milling method or a wet etching method, with the resist pattern used as a mask. As a result, the base electrode is partly exposed to the outside. In this step, a change in structure such as deviation from the inherent composition and change into the amorphous structure takes place in the exposed surface region of the base electrode. Where, for example, the base electrode is made of YBa2Cu3O7, the composition analysis using an XPS indicates that a layer prominently rich in Y is formed in a thickness of about 2 nm in the exposed surface of the base electrode. It is known to the art that the particular layer is amorphous.
Then, in a third step, a high temperature annealing treatment is applied to the two-layer film partially exposing the base electrode to the outside under vacuum or under an oxygen atmosphere. By this heat treatment, the exposed surface region of the base electrode is changed into a layer differing from the inherent structure so as to act as a barrier layer, or forms dislocations or defects in the base electrode and a counter electrode formed in the subsequent step so as to produce the effect of exhibiting the Josephson characteristics. For example, where the base electrode is made of YBa2Cu3O7, the component analysis using an XPS and the structure analysis using an electron microscope indicate that the exposed surface region of the base electrode after the heat treatment noted above contains Y, Ba, Cu and oxygen atoms and that there are a case where a crystal phase of an oxide having a thickness of about 1 nanometer to about several nanometers is grown, and another case where a crystal phase is not present and lattice defects and dislocations are observed in a high density over the entire interface.
In a fourth step, a superconductor layer used as a counter electrode is formed on the two-layer film after the heat treatment. The counter electrode is made of, for example, YBa2Cu3O7. The basic manufacturing process of the Josephson device is finished by the fourth step. However, in order to form the electrode with a high stability, employed are the step of forming a Au layer on the counter electrode and the step of processing the counter electrode into an optional shape.
The manufacturing process described above is directed to a ramp edge type device, and a similar process is employed for the manufacture of the Josephson device of another type such as a laminated type. Also, the manufacturing process described above is directed to the case where the ground plane is not used. However, a process substantially equal to the manufacturing process described above is performed on an insulation film formed on the ground plane.
In order to form a super-high speed logic circuit by using a superconducting device, it is absolutely necessary to make optimum both the critical current (Ic) value of the junction and the inductance (Lc) of the wiring portion, which are basic parameters for describing characteristics of the device. When it comes to, for example, the ramp edge type junction, which is a typical device type, it is desirable for Ic to be about 1 mA and for Lc to be about 0.7xc3x9710xe2x88x9212H or less, in the case where the base electrode has a thickness of 200 nm and a junction width of 4 xcexcm.
Where YBa2Cu3O7 or NdBa2Cu3O7 is used as a material of the base electrode and YBa2Cu3O7 is used as a material of the counter electrode, it was customary to set the temperature for the annealing treatment at a level substantially equal to the substrate temperature in the step of forming the counter electrode. Also, where YBa2Cu3O7 is used as a material of the counter electrode, it is necessary to allow the base electrode to have the (001) orientation in order to lower the Ls value and to manufacture an element having good surface properties. It is generally known in this connection that YBa2Cu3O7 forms the (001) orientation only at a temperatures of 750xc2x0 C. or higher, and that YBa2Cu3O7 forms mainly the (100) orientation at a temperature lower than 750xc2x0 C. Under the circumstances, where the substrate temperature is set at a high level at which the (001) orientation can be achieved, the annealing temperature is rendered excessively high, with the result that the Ic value deviates from the desired value and the flux flow-like characteristics are observed in many cases.
Also, it is known to the art that the Ic value is generally lowered in the case where the annealing temperature and the substrate temperature are lowered, provided that the other conditions are the same. It follows that it is possible to lower the Ic value to a desired level by utilizing the particular phenomenon, i.e., by lowering the substrate temperature, in the annealing step and in the step of forming the counter electrode. However, the particular method causes a large amount of the (100) orientation to be present together in the counter electrode. As a result, a lowering of the critical current (Jc) of the wiring portion, which causes the elevation of the Ls value, occurs so as to adversely affect the high speed operation of the device.
As described above, in the prior art, the range of the substrate temperature causing the counter electrode to have the (001) orientation sufficiently is higher than the range of the substrate temperature capable of realizing a desired Ic value. These two ranges overlap each other only slightly, or do not overlap each other at all. Under the circumstances, it was difficult to simultaneously realize sufficient orienting properties and a desired Ic value.
An object of the present invention is to provide a superconducting device capable of optimizing easily both the critical current value of the junction and the inductance value of the wiring portion and a method of manufacturing the same.
According to a first aspect of the present invention, there is provided a superconducting device, comprising a substrate, a first superconductor layer supported by the substrate and comprising Ln, AE, M and O, wherein Ln represents at least one metal selected from the group comprising Y and lanthanoids, AE represents at least one of alkaline earth metals, and M represents a metal which contains 80 atomic % or more of Cu, and a second superconductor layer comprising a material represented by a formula of (Yblxe2x88x92yLnxe2x80x2y)AExe2x80x22Mxe2x80x23Oz in which Lnxe2x80x2 represents at least one metal selected from the group comprising Y and lanthanoids, AExe2x80x2 represents at least one of alkaline earth metals, Mxe2x80x2 represents a metal which contains 80 atomic % or more of Cu, y represents a value within a range of 0 to 0.9, and z represents a value within a range of 6.0 to 8.0, the first and second superconductor layers forming a junction, and atomic planes each including M and O in the first superconductor layer and atomic planes each including Mxe2x80x2 and Oxe2x80x2 in the second superconductor layer being discontinuous to each other in a position of the junction.
According to a second aspect of the present invention, there is provided a superconducting device, comprising a substrate, a first superconductor layer supported by the substrate and comprising Ln, AE, M and O, wherein Ln represents at least one metal selected from the group comprising Y and lanthanoids, AE represents at least one of alkaline earth metals, and M represents a metal which contains 80 atomic % or more of Cu, and a second superconductor layer comprising a material represented by a formula of (Yb1xe2x88x92yLnxe2x80x2y)AExe2x80x22Mxe2x80x23Oz in which Lnxe2x80x2 represents at least one metal selected from the group comprising Y and lanthanoids, AExe2x80x2 represents at least one of alkaline earth metals, Mxe2x80x2 represents a metal which contains 80 atomic % or more of Cu, y represents a value within a range of 0 to 0.9, and z represents a value within a range of 6.0 to 8.0, at least a portion of the first superconductor layer intervening between the substrate and the second superconductor layer, the first and second superconductor layers forming a junction, atomic planes each including M and O in the first superconductor layer and atomic planes each including Mxe2x80x2 and O in the second superconductor layer being discontinuous to each other in a position of the junction, and a decomposition temperature of the first superconductor layer being higher than a decomposition temperature of the second superconductor layer.
According to a third aspect of the present invention, there is provided a method of manufacturing a superconducting device, comprising subjecting a first superconductor layer, which is supported by a substrate and containing superconductor of oxide, to an etching treatment, subjecting the first superconductor layer to a heat treatment after the etching treatment, and forming a second superconductor layer on the first superconductor layer after the heat treatment, the second superconductor layer comprising a material represented by a formula of (Yblxe2x88x92yLnxe2x80x2y)AExe2x80x22Mxe2x80x23Oz in which Lnxe2x80x2 represents at least one metal selected from the group comprising Y and lanthanoids, AExe2x80x2 represents at least one of alkaline earth metals, Mxe2x80x2 represents a metal which contains 80 atomic % or more of Cu, y represents a value within a range of 0 to 0.9, and z represents a value within a range of 6.0 to 8.0.
It is noted that a construction defined by the above expression of xe2x80x9catomic planes each including M and O in the first superconductor layer and atomic planes each including Mxe2x80x2 and O in the second superconductor layer being discontinuous to each other in a position of the junctionxe2x80x9d includes a construction in which the atomic planes each including M and O in the first superconductor layer and the atomic planes each including Mxe2x80x2 and O in the second superconductor are displaced from each other in a direction parallel to the interface between the first and second superconductor layers, a construction in which an interface deviated from the inherent compositions of these superconductor layers is present between the first and second superconductor layers, and a construction in which an interface that is made amorphous is present between the first and second superconductor layers. When the atomic planes in the first and second superconductor layers are CuO2 planes, the particular construction in question covers, for example, the case where the CuO2 planes in the first superconductor layer and the CuO2 planes in the second superconductor layer are displaced from each other in the position of the junction. Also, an expression xe2x80x9c(abc) orientationxe2x80x9d is used herein later in conjunction with the crystal layer in which the (abc) plane is exposed to the outside. For example, the layer of (001) orientation represents a layer in which the (001) plane is exposed to the outside. Further, the term xe2x80x9cdecomposition temperaturexe2x80x9d or xe2x80x9cdecomposition reaction starting temperaturexe2x80x9d denotes the temperature at which the congruent melt, the peritectic melt or the eutectic melt occurs when an oxide superconductor is heated.
In the first and third aspects of the present invention, at least a part of the first superconductor layer may intervene between the substrate and the second superconductor layer. To be more specific, for example, the first and second superconductor layers may be a base electrode and a counter electrode, respectively. Alternatively, the first and second superconductor layers may be juxtaposed on the substrate.
In the first and third aspects of the present invention, the composition of the first superconductor layer may be different from or equal to the composition of the second superconductor layer.
In the first to third aspects of the present invention, Ln and Lnxe2x80x2 may be the same or different from each other. Also, AE and AExe2x80x2 may be the same or different from each other. Further, M and Mxe2x80x2 may be the same or different from each other.
In the first to third aspects of the present invention, the first superconductor layer may be an oxide superconductor layer comprising a material represented by a formula of LnAE2M3Ox. Also, in this formula, x may be a value within a range of 6.0 to 8.0 or within a range of 6.0 to 7.5.
In the first to third aspects of the present invention, each of AE and AExe2x80x2 may be at least one metal selected from the group comprising Ca, Ba and Sr. Also, the value of z in the formula may fall within a range of 6.0 to 7.5.
In the first to third aspects of the present invention, the superconducting device may be a ramp edge type Josephson device or a laminated type Josephson device. Also, the superconducting device may be another type of Josephson device.
In the third aspect of the present invention, the temperature of the substrate in forming the second superconductor layer may be lower than the temperature of the substrate in applying a heat treatment to the substrate.
Further, in the first to third aspects of the present invention, the superconducting device may include a plurality of junctions. In this case, it suffices for the definitions given above to be satisfied in at least one of these junctions.